1. Field of the Invention
The present invention relates to a digital data processor which handles data comprising words of n-bits wherein address modification for generating (n+m)-bit addresses requires comparatively little hardware and has a high degree of freedom.
2. Description of the Prior Art
In a data processor for n-bit words (hereinafter referred to simply as a processor), and particularly for a value of n in the range from 8 to 32, an instruction is composed in general of 2 to 3 words, and the first word includes an operation code part and a register designation part, while the other words may each be used for designating the location of an operand. Therefore, the memory address is limited to n-bits, and the capacity of the memory unit is limited to 2.sup.n words.
Presently, as a method of expanding a memory address to n+m bits in such a processor, the base register method and the bank method are well known.
In the base register method, a base register of n+m bits is provided for base address modification, and an (n+m)-bit address is obtained by adding the n-bit address given in an instruction with the content of said base register. In this method, memory word capacity can be used effectively since the base address can be selected freely, but on the other hand, it is not suited to a small size processor since a relatively large amount of hardware is required as will be described later. U.S. Pat. No. 3,949,378 discloses one example of the prior art base register method.
In the bank method, an m-bit bank designation register is provided, and an (n+m)-bit address is obtained by concatenating (connecting in series) the content of the bank designation register to the high order side of the n-bit address given in the instruction. In this method, memory word capacity cannot be used effectively since the boundaries of each memory area can be designated only in terms of every 2.sup.n words, however, only a small amount of hardware is required for this concatenation.
The prior art base register method is explained in reference to FIG. 1, wherein, by way of example, and for the subsequent disclosure following, n=16 and m=3. The figure shows a 19-bit instruction counter 1 and a memory space 2 of 2.sup.19 =512K words. In the address 7, designated by the content of the instruction counter 1, the 1st word of a 2-word instruction is stored, and in the adjacent address the 16 bit content of the 2nd word of the same instruction is stored. The effective operand address 6 is obtained by simultaneously adding with a three input adder (1) the 16-bit content 3 of the 2nd word of the instruction, (2) the 16-bit content 4 of the general purpose register designated by the register designation part in the 1st word, and (3) the 19-bit content 5 of the base address register. Said general purpose register is used as the index register.
The meaning of index modification and base address modification is now explained. When plural programs run on one processor on a time sharing basis, the base address indicates the heating address of the memory area in which each program can be used. When a certain program runs, the base address for such a program is placed in the base address register by the control program. In general, the memory area used in each program is a maximum of 64K(=2.sup.16) words, but more areas can also be used if provided for at the time of program generation. When the same sub-routine or list information is used in different parts of a program, an effective address for desired data in the relevant sub-routine or list information can be defined by adding the relative address in the sub-routine or list with the heading address of the relevant sub-routine or list information. In this case, the heading address of the sub-routine is indicated by an index and stored in the index registers. The index registers are generally used also as general purpose registers. In case a plurality of sub-routines or list information is used in one program, it is desirable to prepare all of the heading addresses for the index registers. Because it takes longer to load these heading addresses from the memory each time required, many index registers are required. Since the base address does not change while one program runs, one or two base addresses are sufficient in general.
Although it is possible to perform the index modification and base modification separately by using a 2-input adder, it is not practical because a longer time is taken. Thus a 3-input adder is generally used.
As explained above, the base register method requires a 3-input adder for practical operation and much hardware is required, so that the method is not suited to a small size processor.
The bank method is now explained in reference to FIG. 2, showing a 19-bit instruction counter 11 and a 512K word memory space 12. The 19-bit effective address 16 is obtained with the two input adder by adding (1) the content (the 2nd word of the instruction) of the address next to address 17 with (2) the index register 14 indicated by the register designation part in the 1st word, and by concatenating the content of the 3-bit bank designation register 15 to the upper bit of the sum. In this method, a 2-bit adder can be used and little hardware is required for this concentration, but on the other hand, there are disadvantages.
Here, each area of 2.sup.16 =64K words is called a bank. As described in the explanation of the base register method, when assigning areas within 64K words to be used for each program, it is inevitable to assign one bank to each program. Even if a certain program requires a memory area of less than 64K words, the remaining area becomes useless because it is difficult to make the other program use the remaining area of the assigned bank.